Circuit simulation uses mathematical models, also referred to herein simply as models, to replicate the behavior of an actual circuit. Simulating circuit behavior before actually building the circuit can improve design efficiency by making faulty designs known and providing insight into the behavior of the circuit. In particular, for integrated circuits (ICs), photomasks used to create the ICs are expensive, and breadboarding is generally impractical due to the large numbers of devices or circuit components, e.g., sometimes thousands of transistors, that the circuit contains. Therefore, circuit simulation may be the most time and cost efficient alternative for designing ICs.
Many of the circuit simulation systems used today contain circuit simulation engines, also called analysis engines, that execute software derived from a general-purpose, open source analog circuit simulator called Simulation Program with Integrated Circuit Emphasis (SPICE). SPICE-based circuit simulation systems generally contain a library of models, also referred to herein as compact models, which mathematically describe the behavior of a variety of linear circuit elements such as resistors, capacitors, and inductors and nonlinear circuit elements such as transistors, which can be characterized and modeled as lumped circuit elements. Using these models, a SPICE-based analysis engine can perform a time domain analysis, also referred to herein as a transient analysis, to predict circuit behavior for a wide range of different circuits.
However, the SPICE-based analysis engine can be inept when analyzing electrical systems that include a circuit element for which no compact model exists within the simulation system library and the behavior of which is more accurately modeled as a distributed circuit element based on the physics of the circuit element, such as when simulating an IC package that includes a circuit connected to a multiport interconnect structure. Particularly, a vast shortcoming can be the amount of time associated with simulating an electrical system that contains a multiport interconnect structure. Namely, the time for simulating such a circuit undesirably tends to increase by an order of O(N^3) as the number of ports (N) of the multiport interconnect structure increases.
The present disclosure is illustrated by way of example and is not limited by the accompanying figures, in which like reference numbers indicate similar elements. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present disclosure.
The apparatus and method components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present disclosure so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein. Also, the functions included in the flow diagrams do not imply a required order of performing the functionality contained therein.